Digital Design 5th ed. by Morris Mano

Digital Design - Morris Mano - 5th edition

Authors:

M. Morris Mano and Michael D. Ciletti

Publisher:

Pearson Education, Inc.

Description:

The authors and publisher of this book have used their best efforts in preparing this book. These efforts include the development, research, and testing of the theories and programs to determine their effectiveness. The author and publisher make no warranty of any kind, expressed or implied, with regard to these programs or the documentation contained in this book. The author and publisher shall not be liable in any event for incidental or consequential damages in connection with, or arising out of the furnishing, performance, or use of these programs.

Chapters:

  1. Digital Systems and Binary Numbers
    1. Digital Systems
    2. Binary Numbers
    3. Number‐Base Conversions
    4. Octal and Hexadecimal Numbers
    5. Complements of Numbers
    6. Signed Binary Numbers
    7. Binary Codes
    8. Binary Storage and Registers
    9. Binary Logic
  2. Boolean Algebra and Logic Gates
    1. Introduction
    2. Basic Definitions
    3. Axiomatic Definition of Boolean Algebra
    4. Basic Theorems and Properties of Boolean Algebra
    5. Boolean Functions
    6. Canonical and Standard Forms
    7. Other Logic Operations
    8. Digital Logic Gates
    9. Integrated Circuits
  3.  Gate‐Level Minimization
    1. Introduction
    2. The Map Method
    3. Four‐Variable K-Map
    4. Product‐of‐Sums Simplification
    5. Don’t‐Care Conditions
    6. NAND and NOR Implementation
    7. Other Two‐Level Implementations
    8. Exclusive‐OR Function
    9. Hardware Description Language
  4.  Combinational Logic
    1. Introduction
    2. Combinational Circuits
    3. Analysis Procedure
    4. Design Procedure
    5. Binary Adder–Subtractor
    6. Decimal Adder
    7. Binary Multiplier
    8. Magnitude Comparator
    9. Decoders
    10. Encoders
    11. Multiplexers
    12. HDL Models of Combinational Circuits
  5.  Synchronous Sequential Logic
    1. Introduction
    2. Sequential Circuits
    3. Storage Elements: Latches
    4. Storage Elements: Flip‐Flops
    5. Analysis of Clocked Sequential Circuits
    6. Synthesizable HDL Models of Sequential Circuits
    7. State Reduction and Assignment
    8. Design Procedure
  6. Registers and Counters
    1. Registers
    2. Shift Registers
    3. Ripple Counters
    4. Synchronous Counters
    5. Other Counters
    6. HDL for Registers and Counters
  7. Memory and Programmable Logic
    1. Introduction
    2. Random‐Access Memory
    3. Memory Decoding
    4. Error Detection and Correction
    5. Read‐Only Memory
    6. Programmable Logic Array
    7. Programmable Array Logic
    8. Sequential Programmable Devices
  8. Design at the Register Transfer Level
    1. Introduction
    2. Register Transfer Level Notation
    3. Register Transfer Level in HDL
    4. Algorithmic State Machines (ASMs)
    5. Design Example (ASMD Chart)
    6. HDL Description of Design Example
    7. Sequential Binary Multiplier
    8. Control Logic
    9. HDL Description of Binary Multiplier
    10. Design with Multiplexers
    11. Race‐Free Design (Software Race Conditions)
    12. Latch‐Free Design (Why Waste Silicon?)
    13. Other Language Features
  9. Laboratory Experiments with Standard ICs and FPGAs
    1. Experiment 1: Binary and Decimal Numbers
    2. Experiment 2: Digital Logic Gates
    3. Experiment 3: Simplification of Boolean Functions
    4. Experiment 4: Combinational Circuits
    5. Experiment 5: Code Converters
    6. Experiment 6: Design with Multiplexers
    7. Experiment 7: Adders and Subtractors
    8. Experiment 8: Flip‐Flops
    9. Experiment 9: Sequential Circuits
    10. Experiment 10: Counters
    11. Experiment 11: Shift Registers
    12. Experiment 12: Serial Addition
    13. Experiment 13: Memory Unit
    14. Experiment 14: Lamp Handball
    15. Experiment 15: Clock‐Pulse Generator
    16. Experiment 16: Parallel Adder and Accumulator
    17. Experiment 17: Binary Multiplier
    18. Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs
  10. Standard Graphic Symbols
    1. Rectangular‐Shape Symbols
    2. Qualifying Symbols
    3. Dependency Notation
    4. Symbols for Combinational Elements
    5. Symbols for Flip‐Flops
    6. Symbols for Registers
    7. Symbols for Counters
    8. Symbol for RAM

DownLoadLinks:

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